1. Field of the Invention
In general, the present invention relates to a semiconductor memory device and a technology capable of evaluating a margin insufficiency of the pulse width of a clock signal in the semiconductor memory device and feeding a result of the evaluation back to a design phase with ease for, among other purposes, correction of the layout of the device based on the result. More particularly, the present invention relates to an effective technology applied to semiconductor memory devices including an SRAM (Static Random Access Memory).
2. Description of the Related Art
Documents such as Japanese Patent Laid-open No. 11-306758 have disclosed a semiconductor memory device comprising: a plurality of bit-line pairs provided for columns of a memory-cell array; a data-line pair for transferring data read out from the memory-cell array; a control means for selecting one of the bit-line pairs and for controlling an operation to sustain and stop a state of connection between the selected bit-line pair and the data-line pair in a read operation and a write operation; an equalize means operated during the period in which none of the bit-line pairs are connected to the data-line pair in a read operation to make electric potentials thereof equal to each other; and a write amplifier for driving the data-line pair in accordance with input data in a write operation; wherein, even if the period of the read operation coincides with the period of the write operation, the periods of connection between the selected bit-line pair and the data-line pair in the read operation and the write operation can be adjusted individually and, in addition, the period of connection between the selected bit-line pair and the data-line pair in the read operation can be adjusted independently of the period of connection between the selected bit-line pair and the data-line pair in the write operation and vice versa.
In accordance with the semiconductor memory device described above, since the periods of connection between the selected bit-line pair and the data-line pair in the read operation and the write operation can be adjusted individually and, in addition, the period of connection between the selected bit-line pair and the data-line pair in the read operation can be adjusted independently of the period of connection between the selected bit-line pair and the data-line pair in the write operation and vice versa even if the period of the read operation coincides with the period of the write operation as described above, the period of connection between the selected bit-line pair and the data-line pair in the read operation can be shortened while the period of connection between the selected bit-line pair and the data-line pair in the write operation can be lengthened so that data can be read out from the semiconductor memory device at a high speed and data can be written into the semiconductor memory device with a high degree of reliability.
In addition, documents such as Japanese Patent Laid-open No. 10-188555 have disclosed a technology capable of carrying out a high-speed operation at a high frequency by solving problems caused by mutually repulsive requests for a long data read period and a long data write period through employment of gates entering a conductive state for passing data in the data read and data write periods and employment of a control means for changing the conductive periods of the gates in the data read and data write periods.
In accordance with the technology disclosed in Japanese Patent Laid-open No. 11-306758 (also referred to as patent reference 1), the period of connection between the selected bit-line pair and the data-line pair in the read operation is made different from the period of connection between the selected bit-line pair and the data-line pair in the write operation in order to shorten the period of connection between the selected bit-line pair and the data-line pair in the read operation but lengthen the period of connection between the selected bit-line pair and the data-line pair in the write operation so that data can be read out from the semiconductor memory device at a high speed and data can be written into the semiconductor memory device with a high degree of reliability. In accordance with the technology disclosed in Japanese Patent Laid-open No. 10-188555 (also referred to as patent reference 2), on the other hand, a high-speed operation can be carried out at a high frequency by solving problems caused by mutually repulsive requests for a long data read period and a long data write period. Nevertheless, the technologies do not consider a procedure for evaluating a margin insufficiency of the pulse width of a clock signal and feeding back a result of the evaluation to a design phase for, among other purposes, correction of a layout on the basis of the result. Thus, at some locations in the semiconductor memory device, it is quite within the bounds of possibility that there has been a margin failure, which can otherwise be detected by carrying out an evaluation and/or an analysis. As another problem, it is difficult to verify a pulse width required at the location of the margin failure. In addition, the technologies disclosed in patent references 1 and 2 do not consider adjustment of the pulse width of a clock signal for each of main circuits composing a read in the semiconductor memory device or each of main circuits composing a write in the semiconductor memory device. As a result, it is difficult to improve the performance of the chip by adjusting the pulse width of a clock signal for each of the main circuits.